Paper:
A 145 MHz User-Programmable Gate Array
SIMÕES, E.V., BARONE, D.A.C
6th IEEE International Workshop on Rapid System Prototyping, Chapel Hill, USA, June, 1995. pp. 226-232.
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Abstract:
This work presents the most relevant results derived from the development of a
novel FPGA matrix. Nevertheless its capacity, its highlights are low cost and its ability to
deal with high frequencies. This prototype matrix, named FLECHA, presents some structural
novelties, as a different approach to perform the interconnections among logic cells and
I/O Pads and an internal controller.
One of the major contributions of this work deals with the strategy of placing the
logic cells in rows, allowing a drastic reduction of the number of switches without reducing
interconnection capacity among logic cells and I/O Pads. Following this principle, a new
matrix presenting 600 equivalent gates was built, including 40 logic cells and 40
programmable I/O Pads. The FLECHA matrix is intended to implement simple logic functions as
for fast "glue logic" between processors and memories, reaching an operational frequency of
145 MHz.
Eduardo do Valle Simões,
simoes@icmc.usp.br
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