Jorge Luiz e Silva

The Reconfigurable Dataflow Architecture Research

 

University of Sao Paulo

ICMC Institute of Mathematical Science and Computing Science

Computer Systems Department

SSC Computer System Department

Dr. Jorge Luiz e Silva

LATTES The Brazilian Curriculum Vitae Coordenator of ChipCflow Project

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The Reconfigurable Computing Laboratory

The ChipCflow project has been developed in the Reconfigurable Computig Laboratory LCR at University of Sao Paulo in the Institute of Mathematical Science and Computing Science.
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The ChipCflow Project PDF Print E-mail
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Wednesday, 14 March 2012 12:53

The ChipCflow is a tool to accelerate algorithms using a design of a field programmable gate array (FPGA) as a prototype of a dynamic dataflow architecture. The dynamic dataflow architecture using operators interconnected by parallel buses was implemented. Accelerating algorithms using a dataflow graph in a reconfigurable system shows the potential for high computation rates.
Last Updated ( Wednesday, 14 March 2012 13:35 )
 

SEER GROUP

The Embedded Evolutionary and Robotic Systems group SEER is a team developing researches on Embedded Systems, Evolutionary and Robotics from ICMC-USP works on Intelligent Robotics, Design of Unmanned Aircrafts, Evolutionary Computation, Optimization of Ensembles of Neural Networks for Data Mining, Design of Complex Networks, Dynamic Systems, Fuzzy Systems, Embedded Systems, and Reconfigurable Systems. The ChipCflow project is one of several projects been developed for the SEER group.

Coffee Links

Computer Architecture Homepage - An International Computer Architecture Homepage. FPGA and Programmable Logic Journal - Specific for FPGA´s. EDACafé Newsletter - Several articles of EDA tools. IC Design and Verification Journal - Otimization of Circuits. Electronic Engeneering Journal - Electronic Developments.

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